I. Field of the Invention
The present invention relates in general to the fabrication of a semiconductor device, and more particularly to a method of fabricating twin tube or wells in a silicon substrate.
II. Description of Related Art
In the fabrication of a CMOS device it is frequently desirable to make a complementary or symmetric environment with respect to the NMOS and PMOS devices. In other words, it is frequently necessary to create a suitable N-type region for the PMOS device and a suitable P-type region for the adjacent NMOS device. Each of these N-type and P-type regions is generally referred to as a "tub" or "well".
It is known that formation of such N-wells and P-wells may be achieved by the implantation of an appropriate dopant species, such as boron or phosphorus, into a suitable substrate followed by the high temperature drive-in of the implanted ion.
The process of tub formation generally precedes the step of formation of the active area pattern. However, the step of tub formation does not leave a very clean cut marker of its presence with respect to the subsequent registration overlays, including the active area pattern. This fact necessitates the use of previous masking steps or markers to insure proper alignment. Also, in order to provide a reliable local mask during selective field oxidation, there was a need for a relatively thick nitride over the active area, which in turn prevented the penetration, during ion implant, of phosphorus or boron with adequate control. As a consequence, it is very difficult to achieve formation of twin tubs which are fully complementary and symmetrical.
A method of twin tub formation has been proposed in which oxide layers are used as masks for the various well implant steps. In this known process, an oxide-nitride sandwich is first formed on a substrate to define a first mask through which the N-tub is implanted. Over the portions of the substrate not covered by this mask, a thick oxide is grown to thereby define a second complementary mask through which the P-tub is implanted. Because the formation of these oxide mask layers occurs under high temperature, a certain amount of redistribution of the implanted ions will occur during the formation of the oxide layers used for masking. Thus, it is very difficult to obtain a symmetrical twin tub formation utilizing this process. Moreover, the Bird's beak phenomenon which occurs during formation of the second oxide mask layer provides additional problems in the formation of symmetric N-tubs and P-tubs.
Also, in a CMOS structure, there may be transistors which are in an environment or well of opposite polarity from that of the substrate. For example, the structure may include a combination of a parasitic vertical bipolar device and a parasitic lateral bipolar device of complementary or opposite type. If these devices are spaced closely together, they may enter into a state of high conduction which may be perpetuated even if the stimulus which triggered the high conduction state is removed. This condition, which is generally referred to as "latch-up", is frequently found in CMOS devices having closely adjacent bipolar devices. Such a latch-up condition may drain the power supply of the device and may also overheat the device to the point of destruction.
It is therefore an object of the present invention to provide a new and improved method of fabricating a semiconductor device which is not subject to the foregoing problems and disadvantages.
It is an additional object of the present invention to provide a method of manufacturing a semiconductor device which allows scaling of device geometry down to at least one micron.
It is another object of the present invention to provide a method of manufacturing a semiconductor device which reduces or eliminates parasitic latch-up conditions.
It is a further object of the present invention to provide a method of fabricating a semiconductor device having a high breakdown voltage, low junction capacitance and high speed performance.